Intel's upcoming Nova Lake processors were originally anticipated to include a high-capacity L3 cache. However, recent insights reveal that this significant last-level cache, known as bLLC, will currently be exclusive to unlocked SKUs. Several industry sources have indicated that Intel is creating products specifically tailored to compete with AMD's Ryzen X3D lineup, targeting desktop and mobile platforms first under the Core Ultra branding in the Nova Lake era.

In alignment with previous reports, it is widely expected that Nova Lake configurations with 8 Performance cores and 16 Efficiency cores are the most likely candidates to feature the additional cache. These processors are projected to be classified under the Core Ultra 5 or other higher-end series. It's important to note that definitive evidence regarding whether high-end SKUs with overclocking will include bLLC remains elusive.

At present, the Nova Lake family is tentatively stratified as follows: Core Ultra 9, boasting up to 16 Performance cores, 32 Efficiency cores, and 4 LP-E cores with about 150W thermal design power; Core Ultra 7 with 14 Performance cores, 24 Efficiency cores, and 4 LP-E cores, also rated at 150W; and the Core Ultra 5 segment offering a variety of configurations such as 8 Performance cores, 24 Efficiency cores, and 4 LP-E cores at 150W. The Core Ultra 5 segment includes multiple configurations such as 8P+16E+4 LP-E (125W, reportedly including a bLLC version), 8P+12E+4 LP-E (125W, also available with bLLC), and 6P+8E+4 LP-E (125W, without large cache); alongside the entry-level Core Ultra 3 featuring 4P+8E+4 LP-E and 4P+4E+4 LP-E, both rated at 65W. This lineup mirrors the previously leaked configurations of 52-core, 28-core, and 16-core, although it remains uncertain which will ultimately reach production.

The discussed cache capacity of 144 MB refers to an additional extensive last-level cache stacked on the original architecture. This figure excludes the L2/L3 cache intrinsic to the P and E cores themselves but represents an additional 144 MB of last-level cache situated on the compute tile housing the compute units. Some sources have even speculated that certain Core Ultra 9 models may incorporate a "dual bLLC die" design, potentially elevating total LLC capacity to 180 MB, thereby rivaling or surpassing the cache sizes typical of some current AMD gaming processors leveraging 3D V-Cache technology.

Initially, it was commonly assumed that the bLLC configuration would resemble the cache architecture of Intel's Clearwater Forest, existing as a "system-level cache" within the base die or I/O area to provide a unified cache pool for the entire SoC. However, the latest updates indicate the bLLC resides directly within the compute unit die, functioning as a dedicated last-level cache for that die. This architecture resembles more traditional L3/L4 scaling and is optimized to furnish latency and bandwidth enhancements around specific core clusters, potentially yielding substantial benefits in cache-sensitive gaming and high-performance computing scenarios.

Nearly every source has portrayed the bLLC implementation as Intel's primary strategic move against AMD's X3D series. AMD's use of 3D V-Cache stacking has substantially bolstered gaming performance in select Ryzen 9000X3D models and addressed many previous overclocking impediments, allowing high cache and frequency to coexist harmoniously. Responding to this development, Intel plans to prioritize bLLC for unlocked SKUs, strategically aiming to maximize performance potential in overclockable flagship and value-oriented mid-range models, with future decisions on expanding bLLC to locked models to be guided by market feedback.

According to current roadmaps, AMD also intends to advance 3D V-Cache through the Zen 6 era, steadily iterating upon cache stacking and enhancing gaming performance. Should Intel succeed in stabilizing mass production and leveraging bLLC comprehensively in the Nova Lake generation—bolstered by increased core counts, accelerated memory support, and improved I/O design—a competitive showdown in the "big cache CPU" market segment appears imminent.