Several unreleased Intel Panther Lake "Core Ultra Series 3" processors have surfaced in the PassMark database, namely the Ultra 7 366H, Ultra X7 358H, Ultra 7 365, and Ultra 5 332. The primary takeaway from this data is not just the raw scores but Intel's strategic approach to core layouts in the next-generation mobile processors and the nuanced physical screening strategy impacting frequency and cache configurations.

The Ultra 7 366H and Ultra X7 358H feature 16-core designs with four Cougar Cove P-Cores, eight Darkmont E-Cores, and four Skymont LP-Es. They include 18 MB of L3 cache and 12 MB of L2 cache. The differentiation between these two models lies in their frequency and integrated GPU (iGPU) configuration: the 358H can accelerate up to 4.8 GHz with full 12-cell Xe3 graphics enabled, whereas the 366H reaches about 5.0 GHz but maintains only four GPU cells. This differentiation reflects variations in wafer quality: achieving high-frequency, full-featured GPUs on large modules is complex, leading Intel to recycle crystals graded by model.

The Ultra 7 365 has a reduced 8-core configuration (4+0+4), accommodating only P-Cores and LP-Es. It targets low-cost, low-power platform applications while keeping the 12 MB L3 cache untouched, mirroring the high-end models' 12 MB L2 cache to likely uphold the same front-end scheduling structure, shielding only certain physical units. The Ultra 5 332, with its 6-core arrangement (2+0+2), represents entry-level positioning, featuring a cut-down 6 MB L2 cache, designed to cater to more budget-conscious ranges and optimize wafer utilization.

PassMark’s single-thread (ST) and multi-thread (MT) scores directly result from frequency, core layout, and cache size. For instance, the Ultra 7 366H’s single-thread score of 4217 nearly matches the Ultra 9 285H, despite the latter’s higher acceleration by approximately 400 MHz. This result implies that Panther Lake’s front-end scheduling, branch prediction, and execution unit stacking have undergone significant modifications, enabling high instructions per clock (IPC) competitiveness at lower frequencies. Meanwhile, the 366H’s multithreaded score of 34,386 aligns with the 285H, showcasing the 4P+8E configuration’s capability to fully exploit the architecture under high loads, with sustained scalable performance subject to thermal and power constraints.

The Ultra X7 358H's multithread score (32,288) lags behind the Ultra 7 255H (30,889), despite the 255H’s higher frequencies and additional P-Cores. This discrepancy highlights the generational efficiency advances in architecture, pointing to Intel's strategic enhancement of E-Core participation in mobile processor updates to allow lower-power cores to significantly contribute to multi-thread loads.

The Ultra 7 365’s multithread score of 22,160 outpaces both the Ryzen AI Z2 Extreme and Intel’s Ultra 5 226V, fulfilling its clear role of dominating the mainstream thin-and-light laptop sector with lower core counts, offset by IPC and LP-E architecture scheduling efficiencies. Conversely, the Ultra 5 332 is firmly categorized as a cost-effective entry-level product.

Further leaks, such as the OneXPlayer X1 i, featuring the Ultra 5 338H (12 cores, up to 4.6 GHz), report a Geekbench single-core score of 2428, which trails the Ryzen AI 9 HX 370, but with a superior multicore score of 13,265, outperforming the Strix Point APU. Devices like handheld gaming consoles typically constrain power consumption, making LP-E integration within the scheduling chain crucial for maximizing multi-thread power without increasing power usage, validating this performance outcome.

Intel’s overarching product strategy becomes apparent when synthesizing the configurations across their Ultra 3/5/7/X7/X9 series: a unified 4P architecture with pricing tiers determined by the count of E-Cores and LP-Es, further subdivided by GPU specifications. Higher models keep the 12-cell Xe3, whereas upper-middle models often disable segments of the graphics pipeline. This segmentation strategy broadens crystalline coverage, aligning diverse wafer sizes with respective SKUs to elevate yield efficiency.

While these scores indirectly reflect behavior under unknown power, thermal, and memory configurations, the strategic reflexes in architecture are clear: enhancing reliance on E-Core clusters to boost multi-thread performance, maximizing LP-E scheduling involvement, and surpassing mobile frequency limitations by improving IPC. The definitive performance insights on Panther Lake depend on forthcoming official firmware, power strategies, and OEM cooling solutions, yet current data offers a glimpse into Intel’s recalibrated focus for mobile platform cores.