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AMD May Use N3E Process for Zen 6 CCD and UDNA Architecture GPU, with New IOD Opting for N4C

kyojuro Saturday, January 18, 2025

Last July, AMD held its "AMD Tech Day 2024" event in Los Angeles, where it updated the CPU technology roadmap. For the first time, AMD publicly announced that the Zen 6 series architecture will follow the Zen 5 series, with the Zen 6 series being divided into Zen 6 and Zen 6c, referred to as "large and small cores." However, AMD did not disclose the release date of the Zen 6 series architecture nor confirm the process node that will be utilized.

AMD Tech Day

According to the latest information from the CHH forums, the CCDs for the Zen 6 architecture will be manufactured using TSMC's N3E process, while the new IODs will employ the N4C process.

N3E is TSMC's second-generation 3nm process that reduces the number of EUV mask layers from 25 to 21 compared to the first-generation N3B process, thus lowering production costs and improving yields. Meanwhile, N4C is a new process that TSMC announced in April last year; it is an extension of the N4P technology, featuring an 8.5% reduction in transistor costs and a lower barrier to entry. This allows for expected mass production in 2025. Due to its compatibility with N4P, customers can easily transition to N4C, with benefits such as reduced transistor size and improved yields, making it a cost-effective option for value-oriented products.

At CES 2025, AMD announced the new Ryzen AI MAX series of APUs, codenamed "Strix Halo." These feature two Zen 5 architecture CCDs, offering up to 16 cores, alongside mega-cores with up to 40 RDNA 3.5 architecture CUs. There are rumors that the next-generation Halo will introduce a 3D stacking design to enhance both CPU and GPU performance, although the exact packaging technology will not be revealed until later this year. Notably, the SoCs used in Sony's next-generation gaming consoles will also utilize 3D stacking, though Microsoft's plans remain unclear.

At IFA 2024 in Berlin, Germany, Jack Huynh, AMD's Senior Vice President and General Manager of Compute and Graphics Business Unit, confirmed that in the future, the RDNA architecture for consumers and the CDNA architecture for data centers will be unified into the UDNA architecture. Last year, it was announced that there would be no RDNA 5 architecture, as AMD plans to transition to the UDNA architecture following RDNA 4.

Recent rumors indicate that AMD's UDNA-based GPUs will also utilize the N3E process, and that the flagship big-core GPUs will make a return.

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